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    Basic Computer Architecture

    Motivation

    To introduce the basics of computer architecture from the stand point of a low level language programmer.

    Introduction

    As you may already know, a computer requires both hardware and software in order to properly work. When studying computer programming, whether it be a high level language such as C/C++, Java, etc, it is essential to understand how both the hardware and software components work together to create a working system.

  1. hardware::= input device, CPU, memory, storage, output device

  2. CPU::= Central Processing Unit consists of ALU, registers, cache

  3. ALU::= Arithmetic Logic Unit - where all of the arithmetic instructions are executed

  4. registers::= special purpose memory locations inside the CPU that are used in data manipulation, and there are several types_of_registers found in the CPU. See here for various Intel_80x86_registers found on the 80x86 architecture.

  5. types_of_registers::= Accumulator, General_registers, Index_registers

  6. cache::= special, dedicated high speed memory inside the CPU used for quicker access to more frequently used data or code.

  7. memory::= RAM | Hard disk | External Devices

  8. software::= programs that instruct the CPU what steps to take in a task.

  9. Accumulator::= A general register that is frequently used for storing arithmetic results. The 80x86 uses AL, AH, AX, EAX, RAX as the accumulator.

  10. General_registers::= Registers that are commonly used general purpose computing. Examples of some of the 80x86 general registers are BL, BH, BX, EBX, RBX, CL, CH, CX, ECX, RCX, DL, DH, DX, EDX, RDX, and many more depending on if it is 16 bit, 32 bit or 64 bit programming.

  11. Index_registers::= Registers that are used for array indices or pointer arithmetic. On the 80x86 the index registers are DI, SI, EDI, ESI, RDI, RSI

  12. Intel_80x86_registers::= Intel_8_Bit_Registers, Intel_16_Bit_Registers, Intel_32_Bit_Registers, Intel_64_Bit_Registers, Stack_Pointer_Register, Base_Pointer_Register, Segment_Registers, Instruction_Pointer, Flags_Register

  13. Intel_8_Bit_Registers::= AL, AH, BL, BH, CL, CH, DL, DH,

  14. Intel_16_Bit_Registers::= AX, BX, CX, DX, DI, SI, SP, BP

  15. Intel_32_Bit_Registers::= EAX, EBX, ECX, EDX, EDI, ESI, ESP, EBP

  16. Intel_64_Bit_Registers::= RAX, RBX, RCX, RDX, RDI, RSI, RSP, RBP, R8_R15

  17. Stack_Pointer_Register::= SP, ESP, RSP

  18. Base_Pointer_Register::= BP, EBP, RBP

  19. Segment_Registers::= CS, DS, ES, FS, GS, SS

  20. Instruction_Pointer::= EIP, RIP

  21. Flags_Register::= EFLAGS, RFLAGS, when set, the flag's respective bit is set to one, if not set (or called clear) the flag's respective bit is a zero.

  22. EFLAGS::= EFLAGS register is the 32 bit status register for Intel 80x86 microprocessors that contains the current state of the processor after certain instructions have been executed. Several flags that we will be most concerned about are the following: CF (Carry_flag), PF (Parity_flag), AF (Adjust_flag), ZF (Zero_flag), SF (Sign_flag), TF (Trap_flag), IF (Interrupt_enable_flag), DF (Direction_flag), OF (Overflow_flag)

  23. Carry_flag::= Set when an arithmetic operation has a carry bit go outside the most significant bit, commonly refered to as CF. Bit zero in the FLAGS register is for CF.

  24. Parity_flag::= Set when the least significant byte has an even number of bits, commonly refered to as PF. Bit two in the FLAGS register is for PF.

  25. Adjust_flag::= Also called an Auxillary flag, is set if we have a carry from the low_nibble to the high_nibble, or a borrow from the high_nibble to the low_nibble, in the low-order 8-bit portion of an addition or subtraction operation; commonly refered to as AF. Bit four in the FLAGS register is for AF.

  26. Zero_flag::= Set when an arithmetic operation results in a zero result. This flag is used quite often in conjunction with the cmp dest, source instruction since cmp does evaluates as dest-source=result, and if result is zero, the zero flag is set, a non-zero result clears the zero flag; commonly refered to as ZF. Bit six in the FLAGS register is for ZF.

  27. Sign_flag::= Set when the result of the last arithmetic operation resulted in a value where most significant bit was set. If we have a two's complement interpretation of the result, the sign flag is set if the result was negative number, not set if a positive number; commonly refered to as SF. Bit seven in the FLAGS register is for SF.

  28. Trap_flag::= Allows operation of a processor in single-step mode; commonly refered to as TF. Bit eight in the FLAGS register is for TF. There is not any one instruction that can set or clear the trap flag. It can only be done by the following:

     pushf                    ;Push flags on stack
     mov bp,sp                ;Copy sp to bp
     or word ptr[bp],0100H    ;Set TF flag
     popf                     ;Pop flags

  29. Interrupt_enable_flag::= If set, the CPU will handle maskable hardware interrupts, if not set, the CPU will not handle maskable hardware interrupts. This flag can be cleared or set by CLI, or STI, which are privileged instructions (in protected mode OS'es we may not be allowed to execute this instructions unless our applications are privileged applications; commonly refered to as IF. Bit nine in the FLAGS register is for IF.

  30. Direction_flag::= This flag is used to control the left-to-right or right-to-left direction of string processing. If set, will autodecrement the source index and destination index of MOVS (move string instruction). Think of this as scanning a string from right to left. If not set, will autoincrement the source index and destination index of MOVS (move string instruction). Think of this as scanning a string from left to right. The instructions CLD and STD can be used to clear and set the direction flag, respectively. Commonly refered to as DF. Bit ten in the FLAGS register is for DF.

  31. Overflow_flag::= Set when an arithmetic overflow has occurred in an operation; commonly refered to as OF. Bit eleven in the FLAGS register is for OF.

  32. RFLAGS::= RFLAGS register is the 64 bit status register for Intel 80x86 microprocessors that contains the current state of the processor after certain instructions have been executed.

  33. low_nibble::= the lower four bits of a byte.

  34. high_nibble::= the upper four bits of a byte.

  35. AL::= Lower 8 bits of AX register (Accumulator)

  36. AH::= High 8 bits of AX register (Accumulator)

  37. BL::= Lower 8 bits of BX register

  38. BH::= High 8 bits of BX register

  39. CL::= Lower 8 bits of CX register

  40. CH::= High 8 bits of CX register

  41. DL::= Lower 8 bits of DX register

  42. DH::= High 8 bits of DX register

  43. AX::= 16 bit accumulator register, for 32 bit, see EAX, for 64 bit, see RAX

  44. BX::= 16 bit general purpose register, often used for base address, for 32 bit, see EBX, for 64 bit, see RBX

  45. CX::= 16 bit general purpose register, often used for loop counter, for 32 bit, see ECX, for 64 bit, see RCX

  46. DX::= 16 bit general purpose register, often used as an extra data register, for 32 bit, see EDX, for 64 bit, see RDX

  47. DI::= 16 bit index register used to point to a data destination location, DI means Destination Index, for 32 bit, see EDI, for 64 bit, see RDI

  48. SI::= 16 bit index register used to point to a data source location, SI means Source Index, for 32 bit, see ESI, for 64 bit, see RSI

  49. SP::= 16 bit pointer register pointing to the top of the current stack, for 32 bit, see ESP, for 64 bit, see RSP

  50. BP::= 16 bit pointer register pointing to the base of a data structure, or array, for 32 bit, see EBP, for 64 bit, see RBP

  51. EAX::= 32 bit accumulator register, for 16 bit, see AX, for 64 bit, see RAX

  52. EBX::= 32 bit general purpose register, often used for base address, for 16 bit, see BX, for 64 bit, see RBX

  53. ECX::= 32 bit general purpose register, often used for loop counter, for 16 bit, see CX, for 64 bit, see RCX

  54. EDX::= 32 bit general purpose register, often used as an extra data register, for 16 bit, see DX, for 64 bit, see RDX

  55. EDI::= 32 bit index register used to point to a data destination location, DI means Destination Index, for 16 bit, see DI, for 64 bit, see RDI

  56. ESI::= 32 bit index register used to point to a data source location, SI means Source Index, for 16 bit, see SI, for 64 bit, see RSI

  57. ESP::= 32 bit pointer register pointing to the top of the current stack, for 16 bit, see SP, for 64 bit, see RSP

  58. EBP::= 32 bit pointer register pointing to the base of a data structure, or array, for 16 bit, see BP, for 64 bit, see RBP

  59. RAX::= 64 bit accumulator register, for 16 bit, see AX, for 32 bit, see EAX

  60. RBX::= 64 bit general purpose register, often used for base address, for 16 bit, see BX, for 32 bit, see EBX

  61. RCX::= 64 bit general purpose register, often used for loop counter, for 16 bit, see CX, for 32 bit, see ECX

  62. RDX::= 64 bit general purpose register, often used as an extra data register, for 16 bit, see DX, for 32 bit, see EDX

  63. RDI::= 64 bit index register used to point to a data destination location, DI means Destination Index, for 16 bit, see DI, for 32 bit, see EDI

  64. RSI::= 64 bit index register used to point to a data source location, SI means Source Index, for 16 bit, see SI, for 32 bit, see ESI

  65. RSP::= 64 bit pointer register pointing to the top of the current stack, for 16 bit, see SP, for 32 bit, see ESP

  66. RBP::= 64 bit pointer register pointing to the base of a data structure, or array, for 16 bit, see BP, for 32 bit, see EBP

  67. R8_R15::= 64 bit general purpose registers, R8, R9, R10, R11, R12, R13, R14, R15; have low_order_doubleword, low_order_word, and low_order_byte registers as well.

  68. low_order_doubleword::= The low order 32 bits (0-31) of R8, R9, R10, R11, R12, R13, R14, R15 registers; R8D - R15D

  69. low_order_word::= The low order 16 bits (0-15) of R8, R9, R10, R11, R12, R13, R14, R15 registers; R8W - R15W

  70. low_order_byte::= The low order 8 bits (0-7) of R8, R9, R10, R11, R12, R13, R14, R15 registers; R8B - R15B. Note that Intel uses R8L-R15L in their documentation, but Microsoft Assembler does not recognize these mnemonics.

    . . . . . . . . . ( end of section Basic Computer Architecture) <<Contents | Index>>


Formulae and Definitions in Alphabetical Order